Bachelor and Master Theses

Title: Adaptering av SimpleScalar simulatorn till exekveringsverktyget SWEET
Subject: Computer Science
Level: Advanced
Description: Work description

SWEET is a tool for worst-case execution time (WCET) analysis developed at Mälardalen University. SWEET supports currently two target processors, NECV850E and ARM9. Det suggested work consists of examining the SimpleScalar simulator (a simulator framework used by large parts of today's hardware researchers) and adopt it to SWEET's analysis the timing behaviour of the hardware (low-level analysis). This would allow SWEET to, in a simple way, support many more hardware platforms.

The work consists of examining and documenting the different platforms supported by the SimpleScalar simulator (ARM7, ARM9, MIPS, ...) together with their timing correctness (ie. are they really correctly simulating the timing behaviout of the hardware) and supporting tools (binary code readers, configuration tools for cache- and memory layouts, input- and output formats, etc.). The low-level analysis of SWEET requires that the analysis should be able to exexcute/simulate different basic blocks (ie. sequences of basic blocks) with associated forcing execution information. Such information could be if a cache reference should be a hit or miss, or if the instruction will access a certain type of memory area. The assignment therefore consists of examining how to adapt the SimpleScalar simulation to simulate certain basic blocks with associated execution information. This means probably that parts of the source code of the SimpleScalar needs to be modified for a selection of suitable target platforms.

The work also consists of investigate methods for systematically compare timing values obtained using static analysis or simulation. On this part of the thesis work, the student will work in close cooperation with Johan Stärner, which have large experience in using the SimplarScalar for evaluation- and simulation purposes. To use the SimplarScalar is also interesting from a user perspective, since the *same* tool can be used both in static analysis and simulation of the code, ie. the use only needs to learn one tool.

If time permits, the student can also compare WCET estimates obtained using other WCET analysis tools, such as aiT or Bound-T, with estimates derived using simulation or using the developed
SimplarScalar low-level analysis of SWEET. Alternatively, the student could investigate the possibility to analyze code, with the developed SimplarScalar low-level analysis of SWEET, from some of the industrial partners of the WCET project.

More material to study
  • Homepage of SWEET and the MdH WCET research group:
    http://www.mrtc.mdh.se/projects/wcet
  • Homepage of the SimpleScalar simulator:
    http://www.simplescalar.com/
  • Jakob Engblom's PhD thesis which describes how SWEET's low-level analysis works: http://publications.uu.se/theses/abstract.xsql?isbn=91-554-5228-0
  • Andreas Ermedahl's PhD thesis which describes how SWEET's
    different parts work together: http://publications.uu.se/theses/abstract.xsql?dbid=3502
  • Chronos, another WCET tool which is using the SimpleScalar
    simulator:
    http://www.comp.nus.edu.sg/~rpembed/chronos/
  • Company: IDE
    Start date: 2006-09-01
    Prel. end date: 2007-02-01
    Presentation date: 2007-02-01
    Student: Bahareh Agha Jafari baa05001@student.mdh.se
    IDT supervisor: Andreas Ermedahl
    andreas.ermedahl@mdh.se, +46-21-107334
    Examinator: Bjrn Lisper
    Bjrn Lisper
    bjorn.lisper@mdh.se, +46-21-151709
    Misc: Assistant supervisor: Johan Strner.
    Academic points: 20

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