Bachelor and Master Theses

Title: Multi-resource Server Implementation for Multi-core Architecture
Subject: Computer Science
Level: Advanced
Description: Introduction
Contemporary scheduling of real-time tasks on multi-core architectures is inherently unpredictable, and activities in one core can have negative impact on performance in unrelated parts of the system (on other cores). A major source of such unpredictable negative impact is contention for shared physical memory. In commercially existing hardware, there are currently no mechanisms that allow a subsystem to protect itself from negative impact if other subsystems start stealing its memory bandwidth. For performance-critical real-time systems, overcoming this problem is paramount.
Hierarchical Scheduling Framework (HSF) [1] also called server-based scheduling is used to provide the temporal isolation among components. In hierarchical scheduling the CPU is partitioned into many servers that are scheduled by a global (system-level) scheduler. Using HSF subsystems can be developed and analyzed in isolation from each other. We have experience in implementing a two-level hierarchical scheduling [1, 2] support in an open source real-time operating system, FreeRTOS for single-core architecture. And we have tested our implementations and performed experimental evaluations on AVR-based 32-bit board.

Our goal is to develop a multi-resource server technology that allows a subsystem (i.e. a set of tasks allocated to a server) by extending traditional server-resources with associating a memory-bandwidth to each server [4]. Thus a multi-resource server has both CPU-bandwidth and memory bandwidth allocated to it [3]. Further, we want to achieve this goal using Commercial Off-The-Shelf (COTS) hardware. We need a continuous determination and tracking of the consumed memory bandwidth for this server. We propose to use hardware performance counters to determine memory bandwidth for FreeScale P4080 [5] architecture.
The thesis work demands the following activities: (1) Literature study about hierarchical scheduling; (2) understanding the target hardware and software platforms; (3) The design and implementation of multi-resource server and the test of its correctness and efficiency; (4) Writing the thesis; (5) [optional] Writing and publishing a scientific article based on the thesis.

[1] Rafia Inam, Jukka Mäki-Turja, Mikael Sjödin, S. M. H. Ashjaei, Sara Afshar. ”Support for hierarchical scheduling in FreeRTOS“. In Proc. of the IEEE International Conference on Emerging Technologies and Factory Automation (ETFA 2011), September 2011. Awarded IEEE-IES scholarship for best student paper.
[2] Rafia Inam, Jukka Mäki-Turja, Mikael Sjödin, Moris Behnam. “Hard real-time support for hierarchical scheduling in FreeRTOS”. In Proc. of the 7th International Workshop on Operating Systems Platforms for Embedded Real-Time Applications (OSPERT 11), July 2011.
[3] Rafia Inam, Mikael Sjödin, Markus Jägemar, ”Bandwidth Measurement using Performance Counters for Predictable Multicore Software”. In 17th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'12), WiP, p 1-4, IEEE, Krakow, Poland, September, 2012.
[4] Moris Behnam, Rafia Inam, Thomas Nolte, Mikael Sjödin, “Multi-core Composability in the Face of Memory Bus Contention”, 5th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (CRTS'12), ACM, San Juan, Puerto Rico, December, 2012.
[5] e500mc Core Reference Manual, rev 1, 2012. manual/E500MCRM.pdf.
Proposed: 2012-12-13
Prerequisites: (1) Knowledge about one of the following: real-time systems, embedded systems, or operating systems, (2) Knowledge of C/C++ is valuable.
IDT supervisor: Rafia Inam, 021 103196
Examinator: Mikael Sjödin
Mikael Sjödin, +46 70 288 2829

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