Bachelor and Master Theses

Title: Cache-Partitioning for COTS Multi-core Architecture
Subject: Computer Science
Level: Advanced
Description: Introduction
Contemporary scheduling of real-time tasks on multi-core architectures is inherently unpredictable, and activities in one core can have negative impact on performance in unrelated parts of the system (on other cores). A major source of such unpredictable negative impact is contention for shared physical memory. In commercially existing hardware, there are currently no mechanisms that allow a subsystem to protect itself from negative impact if other subsystems start cache pollution. For performance-critical real-time systems, overcoming this problem is paramount.

Hierarchical Scheduling Framework (HSF) [1] also called server-based scheduling is used to provide the temporal isolation among components. In hierarchical scheduling the CPU is partitioned into many servers that are scheduled by a global (system-level) scheduler. Using HSF subsystems can be developed and analyzed in isolation from each other. For multicore platform, we have experience in implementing a two-level hierarchical scheduling [2, 3] support in Linux. We have developed a multi-resource server technology that allows a subsystem (i.e. a set of tasks allocated to a server) by extending traditional server-resources with associating a memory-bandwidth to each server [1, 3]. Thus a multi-resource server has both CPU-bandwidth and memory bandwidth allocated to it [2]. A continuous determination and tracking of the consumed memory bandwidth is performed using hardware performance counters for Intel architecture on Linux operating system.

Proposal
Our goal is to extend the multi-resource server technology that allows a subsystem to add a third resource to the server i.e. partition cache for each subsystem. Thus a multi-resource server has three CPU-bandwidth, memory bandwidth, and cache-bandwidth allocated to it. We propose to extend our multi-resource server implementation on Linux for the intel architecture.
The thesis work demands the following activities: (1) Literature study about hierarchical scheduling, and cache types and behaviours; (2) understanding the target hardware and software platforms; (3) The design and implementation of cache partitioning and the test of its correctness and efficiency; (4) Writing the thesis; (5) [optional] Writing and publishing a scientific article based on the thesis.

References
[1] Rafia Inam, Mikael Sjödin, Markus Jägemar, ”Bandwidth Measurement using Performance Counters for Predictable Multicore Software”. In 17th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'12), WiP, p 1-4, IEEE, Krakow, Poland, September, 2012.
[2] Moris Behnam, Rafia Inam, Thomas Nolte, Mikael Sjödin, “Multi-core Composability in the Face of Memory Bus Contention”, 5th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (CRTS'12), ACM, San Juan, Puerto Rico, December, 2012.
[3] Rafia Inam, Joris Slatman, Moris Behnam, Mikael Sjödin, Thomas Nolte, “Towards Implementing Multi-resource Server on Multi-core Linux Platform”. In 18th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA'13), WiP, p 1-4, IEEE, September, 2013.
Presentation date: 2015-02-05
Student: Konstantinos Konstantopoulos kks12001@student.mdh.se
IDT supervisor: Rafia Inam
rafia.inam@mdh.se, 021 103196
Examinator: Mikael Sjödin
Mikael Sjödin
mikael.sjodin@mdh.se, +46 70 288 2829

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2015-03-13, 16:28


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