I'm currently a hibernated PhD student. Between June 1998 and October 2002 I was doing research at 50% of my work. The area was on computer architecture and real-time with the focus on cache memories. The SARA project funded the research. Maybe I will resume my research later or do some non-funded black research in the background, but at the moment no new reserach is ongoing. You're of course welcome to ask questions if you have any!

More about my research can be found in the MRTC database

• Filip Sebek, "Instruction cache memory issues in real-time systems"
  Licentiate thesis presented October 11:th 2002, Mälardalen University. Opponent was Axel Jantsch (KTH) and examinator was Lars Wanhammar (LiTH). Thesis in [pdf][bibtex] and presentation in [powerpoint].
  
  
• Filip Sebek, "The real cost of task pre-emption - measuring real-time-related cache performance with a HW/SW hybrid technique", MRTC Technical report 02/58, August 2002. [pdf][bibtex]
  
  
• Filip Sebek and Jan Gustafsson, "Determining the Worst-Case Instruction Cache Miss-Ratio"
  IEEE/ACM Workshop On Embedded System Codesign (ESCODES'02), San José, September 24, 2002 [pdf] [bibtex]
  
  
• Filip Sebek, "Measuring Cache Related Pre-emption Delay on a Multiprocessor Real-Time System"
  IEEE/IEE Real-Time Embedded Systems Workshop, London, December 3, 2001 [pdf] [bibtex]
  
  
• Filip Sebek, "The state of the art in Cache Memories and Real-Time Systems"
  Technical Report MRTC 01/37, October 2001 [pdf] [bibtex]
  
  
• Filip Sebek, "Cache Memories - an unpredictable hardware component in RTS"
  internal report in poster format, January 1999 [pdf]