Bachelor and Master Theses

To apply for conducting this thesis, please contact the thesis supervisor(s).
Title: Offline Scheduling for Partitioned Multi-core Real-Time Systems with TDMA Arbitrated System Bus
Subject: Embedded systems
Level: Advanced
Description: A large share of innovation in modern embedded system applications can be attributed to computer-controlled functionality. Traditionally, this functionality is realised by software that runs on single-core embedded processors. However, the advanced features and new customer requirements in modern vehicles require new levels of computation power. Multi-core embedded systems are being considered as a promising solution to support such advanced and data-intensive functionality. Apart from the computational requirements, these systems are often required to be predictable, i.e., it should be possible to prove or demonstrate that all timing requirements specified on these systems are satisfied. The challenge of supporting predictable execution of the software on multi-core embedded systems is more difficult to deal with compared to single-core embedded systems, due to an additional data-propagation delay caused by shared resources, e.g., the system bus. One way to support predictable execution in multi-core embedded systems is to use a time-triggered schedule for the system bus. However, such a solution can result in large inter-core data propagation delays in the worst-case scenario.

This thesis focuses on developing new approaches based on heuristics to create time-triggered schedules for each core (i.e. partitioned scheduling). Each job of a task follows the Read-Execute-Write semantic, where shared memory is only accessed during Read and Write phases. The generated schedules therefore must guarantee that read and write phases are only scheduled at times when the respective core has access to the system resources (due to the time triggered scheduling of the bus). In addition, task chains that are specified in the system are often subject to delay constraints on the data propagation through instances of the tasks. These constraints need to be met by the generated schedule, possibly over core-boundaries.

The goal is to develop a scheduling tool prototype that implements these approaches and conduct a performance evaluation using the prototype.

Expected main results:
1- Literature review and exploration of related schedules in the state of the art and practice
2- Developing scheduling heuristics.
3- Develop and implement tool prototypes of the heuristics.
4- Perform an extensive evaluation of the heuristics under different scenarios.
5- Write the thesis report.

The thesis can be adapted for 1-2 students for 15 or 30 CP

References:
[1] L. Hasanagic, T. Vidovic. Tighter Inter-core Delays in Multi-core Embedded Systems under Partitioned Scheduling, Master Thesis, Mälardalen University, 2020, Available: http://www.diva-portal.org/smash/get/diva2:1438299/FULLTEXT01.pdf
[2] L. Hasanagic, T. Vidovic. S. Mubeen, M. Ashjaei, M. Becker, Optimizing Inter-Core Data-Propagation Delays in Industrial Embedded Systems under Partitioned Scheduling, 26th Asia and South Pacific Design Automation Conference, 2021. Available: http://www.es.mdh.se/publications/5912-

Supervisor(s): Saad Mubeen (MDH); Matthias Becker (KTH)
Examiner: TBD
Start date:
End date:
Prerequisites: • Programming knowledge in C or Java
• Knowledge about real-time systems (Embedded Systems II course at MDH)
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