Title: Load Balancing Workloads Through DRAM Bank Partitioning
Subject: Computer science
Level: Basic
Description: Reliability has long been seen as one of the major bottlenecks when incorporating
multi-core systems in embedded environments. The many different shared hardware
resources can cause unwanted memory contention, which is caused by different processes
competing for the same memory. However, measures such as partitioning can be taken in
order to guarantee exclusive ownership of shared hardware resources.
Hardware partitioning is a technique that partitions hardware on the chip without
any software support and can be both robust and effective. Hardware partitioning is
however not always applicable to general Commercial Off the Shelf (CoTS) hardware
platforms such as Intel, since there may be a lack of support for such functionalities.
Another technique that can be used, is the software based partitioning method
page-coloring. Page-coloring isolates hardware resources using software techniques. Itis a
much more general approach since it is applicable to all systems using a feasible Linux
kernel. The page-coloring technique is applicable to both DRAM and cache memory.
In this work, we will focus on investigating the page-coloring technique for DRAM
memories, called DRAM bank partitioning. DRAM bank partitioning is used for over-writing
the memory translations from the virtual to the physical memory, in order to reduce
memory contention on the DRAM memory.
Start date: 2018-03-26
End date: 2018-05-23
IDT supervisors: Jakob Danielsson
Examiner: Masoud Daneshtalab